Block Level Physical Design of Interfacing Module in RISC Core
Siddalinga Aland1, V. Venkateswarlu2, Rohith B.R3

1Mr. Siddalinga Aland VLSI Design and Embedded Systems, visvesvaraya Technological University/ UTL Tech. ltd., VTU / UTL Technologies, Bangalore, India.
2Dr. V.Venkateswarlu, VLSI Design and Embedded Systems, visvesvaraya Technological University/ UTL Tech. Ltd., VTU / UTL Technologies, Bangalore, India.
3Mr. Rohith B. R, VLSI Physical Design, SMARTPLAY Technologies Ltd, Bangalore, India.
Manuscript received on August 01, 2012. | Revised Manuscript received on August 05, 2012. | Manuscript published on August 10, 2012. | PP: 46-51 | Volume-1 Issue-3, August 2012. | Retrieval Number: C0216071312/2012©BEIESP
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Abstract: The physical design plays a major role in implementing the circuit and logic cells physically, because physical devices and interconnecting materials will have its own parasitic resistances and capacitances. Placement and Routing (PNR) flow involves proper placement and routing the interfacing module including majorly PCI and SDRAM. In this project work digital cells called standard cells and macro are placed with minimum congestion of 3% in a block. And routing is done by keeping in mind the manufacturability by utilizing non default rule (NDR) design rules. The clock tree network is built by using the H-Tree network topology. The power network is synthesized with higher metal layers available in technology node. This project is implemented in TSMC 120nm technology, which has 7 metal layers but as this project is block level so 6 metal layers are used for routing. The clock frequency of block system is 250MHz is used as the main clock, peripheral clocks and generated clock of 133MHz. The GDSII format of layout is generated with no violations.
Keywords: Placement, Routing, Utilizing, Manufacturability