Hardware Implementation of ZUC Stream Cipher
Praneet .R. Shah1, Naganath.B.Hulle2

1Mr. Praneet R Shah, ME VLSI & Embedded System, GHRIET Wagholi, Pune (Maharashtra), India.
2Prof. N.B. Hulle, ME E&T’C, GHRIET Wagholi, Pune (Maharashtra), India.
Manuscript received on 8 August 2013 | Revised Manuscript received on 18 August 2013 | Manuscript Published on 30 August 2013 | PP: 89-91 | Volume-3 Issue-3, August 2013 | Retrieval Number: C1117083313/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Stream ciphers are more efficient as compared to block ciphers, when implemented in hardware environment, like Field Programmable Gate Array (FPGA). In this paper a high throughput hardware implementation of ZUC stream cipher is presented. ZUC is a stream cipher that forms the heart of the 3GPP confidentiality algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3. This algorithm offers reliable security services in Long Term Evolution networks (LTE), which is a candidate standard for the 4G network. A detailed hardware implementation is presented in order to reach satisfactory performance results in LTE systems. The design is being coded using VHDL language and for the hardware implementation, a XILINX Virtex-5 FPGA is used [1][2].
Keywords: 3GPP, FPGA, Long Term Evolution Networks Security, ZUC.

Scope of the Article: Security and Privacy