Design and Implementation of Arithmetic Coder Used in SPIHT
K. Harika1, K. V. Ramana Reddy2
1K.Harika, Department of VLSI Design and Embedded Systems, Visveswaraiah Technological University, Bangalore (Karnataka), India.
2K.V.Ramana Reddy, Assistant Professor, Department of VLSI Design and Embedded Systems, Visveswaraiah Technological University, Bangalore (Karnataka), India.
Manuscript received on 8 August 2013 | Revised Manuscript received on 18 August 2013 | Manuscript Published on 30 August 2013 | PP: 119-124 | Volume-3 Issue-3, August 2013 | Retrieval Number: C1127083313/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper Set Partitioning in Hierarchical Trees (SPIHT) algorithm for image compression is proposed with a arithmetic coder thereby it compresses the Discrete Wavelet Transform decomposed images. This architecture is advantageous from various optimizations performed at different levels of arithmetic coding from higher algorithm abstraction to lower circuit implementation. SPIHT has straightforward coding procedure and requires no tables which make a SPIHT algorithm an appropriate one for low cost hardware implementation. In order to avoid rescanning the wavelet transformed coefficients a breadth first search SPIHT without lists is used instead of SPIHT with lists. With the help of Breadth First search high speed architecture is achieved. Dedicated circuit such as common bit detector is used for loop unrolling the renormalization stage of arithmetic coding. Critical path in the architecture are shortened by employing Floating point multiplier and carry look ahead adder. Design has been implemented on Spartan 6 FPGA.
Keywords: Arithmetic Coding, Common Bit Detection (CBD) Circuit, Discrete Wavelet Transform (DWT), Set Partitioning In Hierarchical Trees (SPIHT).
Scope of the Article: Digital System and Logic Design