A Comparison of Piplined and Parallel CORDIC Architecures
Mohamed.M.Elgazzar1, Mahmoud Maher El-Sayed Mohammed2

1Mohamed. M. Elgazzar, Associate Professor, Department of Computer Science and Information Systems, Higher Institute of New Cairo, Egypt.
2Mahmoud Maher El-Sayed Mohammed, Engineering Collage, Cairo University, Giza, Egypt.
Manuscript received on 05 January 2019 | Revised Manuscript received on 13 January 2019 | Manuscript published on 30 January 2019 | PP: 50-52 | Volume-8 Issue-3, January 2019 | Retrieval Number: C2569018319/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Coordinate Rotation Digital Computer (CORDIC) is efficient and simple algorithm that is used to calculate the trigonometric and hyperbolic functions. The CORDIC is used in multiple applications like hardware multiplier in the field programmable gate array (FPGA) or in simple microcontroller. The advantage of the CORDIC is that it uses only shift and add operations. The CORDIC can be implemented in different architectures like the parallel (or combinational) architecture, pipelined architecture, and iterative architecture. We want to know what is the pros and cons for every architecture, so our research will be very important to the integrated circuit (IC) designer. The designer should know the advantages of each architecture to choose the suitable architecture for his design. In this paper we will make comparison between pipelined and parallel CORDIC architectures. The comparison steps are implementing the parallel and the pipelined CORDIC architectures in Verilog register transfer level (RTL) codes, then simulating these two Verilog codes using Modelsim. The both architectures will be simulated using the same test sequence. The sequence flow is inserting angles from zero degree to ninety degree and compare the outputs which are cosine and sine for the inserted angle to the expected values. The test sequence will be the same for both architectures. This will make the same simulation environment for the two architectures. From simulation results, we can expect the parallel CORDIC is more efficient in the initial delay, area, power consumption, and the pipelined CORDIC is more efficient in the clock frequency, critical path.
Keyword: CORDIC, E. Volder, FPGA, Parallel CORDIC, Pipelined CORDIC.
Scope of the Article: Parallel Computing