Design of Completion Detectors in Asynchronous Communication System
Norhuzaimin Julai1, Shamsiah Suhaili2, Yonis M Yonis Buswig3
1Norhuzaimin Julai*, Faculty of Engineering, Universiti Malaysia Sarawak(UNIMAS), Kota Samarahan, Sarawak, Malaysia.
2Shamsiah Suhaili, Faculty of Engineering, Universiti Malaysia Sarawak(UNIMAS), Kota Samarahan, Sarawak, Malaysia.
3Yonis M.Yonis Buswig, Faculty of Engineering, Universiti Malaysia Sarawak(UNIMAS), Kota Samarahan, Sarawak, Malaysia.
Manuscript received on December 12, 2019. | Revised Manuscript received on December 24, 2019. | Manuscript published on January 10, 2020. | PP: 3329-3334 | Volume-9 Issue-3, January 2020. | Retrieval Number: C8576019320/2020©BEIESP | DOI: 10.35940/ijitee.C8576.019320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In digital design, there are two types of design, synchronous design and asynchronous design. In synchronous design, global clock is one of the main system that consume a lot of power. The power in synchronous design is consumed by clock even if there is no data processing take place. The asynchronous design that depends on data is clockless and as far as the power is concerned, asynchronous design does not consume much power compared with synchronous design and this really make asynchronus design the preffered choice for low power consumption. Besides having low power consumption, there are many advantages of aynchronous design compared with synchronous design. This paper proposed new dual rail completion detector (CD), 3-6 CD, 2-7 CD and 1-4 CD for on-chip communication that are used widely in an asynchronous communication system. The design of CD is based on the principle of sum adder. The circuit is designed by using Altera Quartus II CAD tools, synthesis and implementation process is executed to check the syntax error of the design. The design proved to be successful by using asynchronous on-chip communication in the simulation.
Keywords: Asynchronous, Converter, Completion detector, Quartus II
Scope of the Article: Communication