Hardware-Based Physical Layer Security Solutions and Algorithms for Iot Devices on FPGA Platform
Bharathi R1, N. Parvatham2
1Bharathi R.*, Research Scholar, PRIST University, Thanavur, Tamil Nadu, India.
2N. Parvatham, Associate Professor, PRIST University, Thanjavur, Tamil Nadu, India.
Manuscript received on December 14, 2019. | Revised Manuscript received on December 23, 2019. | Manuscript published on January 10, 2020. | PP: 2128-2132 | Volume-9 Issue-3, January 2020. | Retrieval Number: C8752019320/2020©BEIESP | DOI: 10.35940/ijitee.C8752.019320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Physical Layer Security mechanism has emerged as a powerful concept that can provide high-level security and can even replace encryption oriented schemes, which necessitate various difficulties and practical challenges for future communication systems (e.g., IoT). Therefore, the critical goal of this work is to enhance the security performance at IoT and prevent the network from various eavesdropping attacks. In this Manuscript, analyze the hardware-based Physical Layer Security solutions and suitable cryptographic Algorithms for IoT applications. The Cryptographical Algorithms include AES, DES, Light Encryption Devices (LED), PRESENT, Extended Tiny Encryption Device (XTEA) are analyzed on the Hardware platform. The Hardware constraints like Area, Frequency, Latency Throughput, and efficiency are evaluated on FPGA devices.
Keywords: Cryptography, Internet of Things (IoT), Physical Layer Security, FPGA, Lightweight Algorithms
Scope of the Article: Internet of Things (IoT)