A Hierarchical Design of 128 Bit Carry Lookahead Adder in 65 nm CMOS Technology
Kishore Prabhala1, Prabhandhakam Sangameswara Raju2
1Kishore Prabhala*, Research Scholar, EEE PhD, Rayalaseema University, Kurnool, Senior Member IEEE, Principal, PLNM Degree College, Opposite Acharya Nagarjuna University Mens Hostel, Nagarjuna Nagar , Guntur Dist., AP, India.
2Prof. Prabhandhakam Sangameswara Raju, EEE, SVU Engineering College, Sri Venkateswara University, Tirupati., AP.
Manuscript received on December 13, 2019. | Revised Manuscript received on December 22, 2019. | Manuscript published on January 10, 2020. | PP: 2643-2648 | Volume-9 Issue-3, January 2020. | Retrieval Number: C8757019320/2020©BEIESP | DOI: 10.35940/ijitee.C8757.019320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: As One Giga Hertz microprocessors power mobiles, laptops, tablets and personal computers in last few years, there is a massive need to reduce the number cycles to do addition which plays a significant role in Arithmetic Logic Unit (ALU) or Digital Signal Processing (DSP). The complexity of carry propagation is the critical variable once the designs requires addition over 32 bits. A hierarchical design has been developed to find Carry out at 16-bit stage from Propagate and Generate techniques from a 4-bit stage of Carry Lookahead Adder (CLA), so called Carry Lookahead Logic (CLL). Four blocks of CLL have been used to create another CLL block at a 16-bit level and similarly at 64 bit level and 128 bit level. A 65 nm CMOS technology library from Microwind used to simulate from logic to circuit level for the hierarchical design of 128 bit CLA and compared with 90 nm technology
Keywords: 65 nm CMOS, Carry Lookahead Adder, Hierarchical, Microwind, and VLSI.
Scope of the Article: Resent Engineering and Nano Technology