A Concurrent Self Repair Scheme for Defects in Random Access Memories
Sandeep Sivvam1, Solomon Gotham2

1Sandeep Sivam, M.Tech ECE Department, JNTU Kakinada University, Kaushik College of Engineering, Visakhapatnam, India.
2Solomon Gotham, Professor & Head, Dept. of ECE, Kaushik College of Engineering , Visakhapatnam, India.

Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 44-46 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0248081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Built-in self-repair (BISR) techniques are widely used for repairing embedded random access memories (RAMs). One key component of a BISR module is the built-in redundancy-analysis (BIRA) design. This paper presents an effective BIRA scheme which executes the 2-D redundancy allocation based on a 1-D local bitmap. Two BIRA algorithms for supporting two different redundancy organizations are also proposed. Simulation results show that the proposed BIRA scheme can provide high repair rate (i.e.,the ratio of the number of repaired memories to the number of defective memories) for the RAMs with different fault distributions. Experimental results show that the hardware overhead of the BIRA design is only about 2.9% for an 8192 64-bit RAM with two spare rows and two spare columns. The design is implemented on Xiliinx Spartan3E FPGA and the device used 532 flip-flops out of 3840 available and 439 LUT’s out of 3840 and the number of IO blocks used is 13. Moreover, the time overhead of redundancy analysis is very small. Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Total power utilized by the device was0.041mW. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. The BIRA module executes the proposed redundancy analysis (RA) algorithm for RAM with a 2-D redundancy structure, i.e., spare rows and spare columns. 
Keywords: BIRA, REBIRA.