Single Dictionary based Cache Compression and Decompression Algorithm
Prasad Munasa1, P. Jayanagalakshmi2

1Prasad Munasa, M.Tech Ece Department, JNTU Kakinada University, Kaushik College of Engineering, Visakhapatnam, India.
2P. Jayanagalakshmi, Asst. Professor , Dept. of Ece, Kaushik College of Engineering , India.

Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 51-55 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0250081412/2012©BEIESP
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Abstract: Computer systems and micro architecture researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. All work on cache compression, has made unsubstantiated assumptions about the performance, power consumption, and area overheads of the proposed compression algorithms and hardware. It is not possible to determine whether compression at levels of the memory hierarchy closest to the processor is beneficial without understanding its costs. Furthermore, as we show in this paper, raw compression ratio is not always the most important metric. In this paper, we present a lossless compression algorithm that has been designed for fast on-line data compression, and cache compression in particular. The algorithm has a number of novel features tailored for this application, including combining pairs of compressed lines into one cache line and allowing parallel compression of multiple words while using a single dictionary and without degradation in compression ratio. Apart from that we reduced the proposed algorithm to a register transfer level hardware implementation on Xilinx xc3s500E fpga permitting performance, power consumption, and area estimation. The total power consumption of the device was estimated to be 0.081W.
Keywords: Cache Compression, Pair Matching, Parallel Compression, Hardware Implementation.