Noise-Tolerant Circuits in Deep-Submicron using Delay Pass Transistor Circuit
Hanan A. Hosni Mahmoud

Hanan A. Hosni Mahmoud, Department of Computer Science, College of Computer and Information Sciences, Princess Nourah bint Abdulrahman University, Riyadh, KSA Dept. of Computer and Systems Engineering, Faculty of Engineering, University of Alexandria, Egypt.

Manuscript received on January 13, 2020. | Revised Manuscript received on January 26, 2020. | Manuscript published on February 10, 2020. | PP: 383-388 | Volume-9 Issue-4, February 2020. | Retrieval Number: D1404029420/2020©BEIESP | DOI: 10.35940/ijitee.D1404.029420
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Abstract: In this paper, we propose a technique to increase the noise tolerance significantly over that of the existing circuit components and design styles. The paper proposes noise tolerance in the discrete, yet interrelated, areas of computational components design, powerless/groundless design style, dynamic circuit style, and memory design. Our results indicate a huge gain in noise-tolerance over the existing circuits and styles. The circuit components and design styles, developed by the technique, are integrated into architectures to study and demonstrate the combined effects of the techniques. This will be in addition to observing and analyzing the individual noise-tolerances of each components and circuit styles developed. We are proposing the limiter pass transistor technique, which is a new method to immune dynamic circuits from noise. Our proposed technique demonstrates 5.9X times gain in noise tolerance over the convectional dynamic circuit and 3.0 X gains over the best known method in the literature. Based on the preliminary proposed technique, we expect to come with dynamic circuit styles that can provide an order of magnitude more noise immunity. 
Keywords: Noise Immunity, Efficient NAND, VLSI design, CMOS
Scope of the Article:  Nanometer-scale integrated circuits