Estimation and Correction of Sampling Time Offsets in Tiadcs using Optimization Algorithm
M. V. N. Chakravarthi1, B. Chandramohan2

1M. V. N. Chakravarthi*, Electronics & Communication Engineering, Acharya Nagarjuna University, Guntur, India.
2Dr. Bhuma Chandramohan, Electronics & Communication Engineering, Bapatla Engineering College, Bapatla, India.
Manuscript received on January 12, 2020. | Revised Manuscript received on January 22, 2020. | Manuscript published on February 10, 2020. | PP: 1217-1222 | Volume-9 Issue-4, February 2020. | Retrieval Number: D1523029420/2020©BEIESP | DOI: 10.35940/ijitee.D1523.029420
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Abstract: In recent communication technologies, very high sampling rates are required for rf signals particularly for signals coming under ultra high frequency (UHF), super high frequency (SHF) and extremely high frequency (EHF) ranges. The applications include global positioning system (GPS), satellite communication, radar, radio astronomy, 5G mobile phones etc. Such high sampling rates can be accomplished with time-interleaved analog to digital converters (TIADCs). However, sampling time offsets existing in TIADCs produce non-uniform samples. This poses a drawback in the reconstruction of the signal. The current paper addresses this drawback and offers a solution for improved signal reconstruction by estimation and correction of the offsets. A modified differential evolution (MDE) algorithm, which is an optimization algorithm, is used for estimating the sampling time offsets and the estimated offsets are used for correction. The estimation algorithm is implemented on an FPGA board and correction is implemented using MATLAB. The power consumption of FPGA for implementation is 57mW. IO utilization is 27% for 4-channel TIADCs and 13% for 2-channel TIADCs. The algorithm estimated the sampling time offsets precisely. For estimation the algorithm uses a sinusoidal signal as a test signal. Correction is performed with sinusoidal and speech signals as inputs for TIADCs. Performance metrics used for evaluating the algorithm are SNR (signal to noise ratio), SNDR (signal to noise and distortion ratio), SFDR (spurious-free dynamic range) and PSNR (peak signal to noise ratio). A noteworthy improvement is observed in the above mentioned parameters. Results are compared with the existing state of the art algorithms and superiority of the proposed algorithm is verified. 
Keywords:  FPGA, Fractional Delay filter, MDE Algorithm ,Sampling Time offset, Time-Interleaved ADCs,
Scope of the Article: Design Optimization of Structures