Latency Minimization using Mesochronous Scheduling in MPSoC Operation
Sukanya.K1, G. Laxminarayana2

1Sukanya.K*, Department of E.C.E, TKR College of Engineering and Technology, Ranga Reddy.
2G. Laxminarayana Department of E.C.E, Anurag College of Engineering, Ranga Reddy, Telangana.
Manuscript received on January 12, 2020. | Revised Manuscript received on January 22, 2020. | Manuscript published on February 10, 2020. | PP: 2934-2942 | Volume-9 Issue-4, February 2020. | Retrieval Number: D1949029420/2020©BEIESP | DOI: 10.35940/ijitee.D1949.029420
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Abstract: High speed computing is the upcoming challenge for next generation applications. To cope with high speed operations, new processing architectures are evolving. Multi processor design is one optimal design approach for such need. In the design development of multi processor unit, MultiProcessor System-on-Chip (MPSoC) has an outcome in the domain of VLSI design. MPSoC are designed to process multiple instructions and data handling simultaneously. The parallel processing feature make this unit faster and optimal design for upcoming applications. However, MPSoC operations have a latency issue in clock allocation and resource utilization, which effects the processing efficiency and introduces delay and resource overhead in MPSoC interface. This paper outlines a Mesochronous operation in MPSoC design for minimizing latency in clock allocation and resource allocation, hence improving the speed of operation. 
Keywords: Latency Minimization, MPSoC Design, Mesochronous Operation, VLSI Design.
Scope of the Article: Operational Research