Implementation of 64 Bit Complex Floating Point Multiplier on FPGA using Vedic Mathematics Sutra- Urdhva Tiryagbhyam
N. Janardan1, T. Lakshman Sai Kumar2, Velmathi Guruviah3
1N. Janardan*, M. Tech VLSI School of electronics Engineering, VIT Chennai, Tamil Nadu, India.
2T. Lakshman Sai Kumar, M. Tech VLSI School of electronics Engineering, VIT Chennai, Tamil Nadu, India.
3Velmathi Guruviah, professor, School of electronics Engineering, VIT Chennai, Tamil Nadu, India.
Manuscript received on January 12, 2020. | Revised Manuscript received on January 22, 2020. | Manuscript published on February 10, 2020. | PP: 2986-2989 | Volume-9 Issue-4, February 2020. | Retrieval Number: D2106029420 /2020©BEIESP | DOI: 10.35940/ijitee.D2106.029420
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Multipliers play crucial role in present days in the area of digital signal processing and in communication systems applications. The entire system performance depends on speed area and power of the multipliers. In our paper, we developed a 64×64 bit complex floating-point multiplier with 64bit IEEE 754 format multipliers having less delay. Vedic multiplier of ripple carry adder based is suggested for mantissa multiplication in IEEE 754 format. Suggested Vedic multiplier uses historic Vedic Indian mathematics sutra called Urdhva Tiryagbhyam for Vedic multiplication. The architecture Proposed for 64×64 bit complex floating-point multiplier is in Xilinx ISE 14.2 FPGA navigator in Verilog HDL. Eventually, the outcomes of the suggested multiplier will differentiate with traditional booth multiplier and array multiplier which represents clearly that complex multiplication using suggested architecture gives less delay, power and low area.
Keywords: IEEE 754 Format, Vedic Mathematics, Urdhva Tiryagbhyam, field Programmable gate Array (FPGA), Booth Multiplier, Array Multiplier.
Scope of the Article: Applied Mathematics and Mechanics