FPGA Implementation of Logarithmic Multiplier
P. Anusha1, G. Kalpana2, T. Vigneswaran2
1Anusha. P, Department of Electronics Engineering, VIT Chennai (Tamil Nadu), India.
2Kalpana G, Department of Computer Science, FSH, SRM Institute of Science and Technology, Kattankulathur (Tamil Nadu), India.
3Vigneswaran T, Department of Electronics Engineering, VIT Chennai (Tamil Nadu), India.
Manuscript received on 05 February 2019 | Revised Manuscript received on 13 February 2019 | Manuscript published on 28 February 2019 | PP: 446-449 | Volume-8 Issue-4, February 2019 | Retrieval Number: D2740028419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: logarithmic multiplier is the vital procedure mainly for DSP, image processing and 3-D graphic applications. Log multiplier converts the multiplication into addition; hence it will reduce the number of computation steps to speed up the multiplication. In multiplication process, the reduction of partial products contributes most to the overall delay, power and area. Adder Compressors are employed to reduce the latency of this step. Analysis is done by coding the designs in HDL and synthesized with Xilinx ISE 14.7 using Virtex6 or spartan3 series of FPGA. Optimized architectures are synthesized using Encounter RTL Compiler Tool in Cadence and obtained the reports on power and area. The results indicate the better speed high performance and overall efficiency of logarithmic multiplication.
Keyword: LNS (Logarithmic Number Systems), Arithmetic Circuit, Multiplication, LUT, Mitchell.
Scope of the Article: Nanometer-Scale Integrated Circuits