A Framework for Logically Reconfigurable Cache Memory for High Performance and Low Power Consumption in Modern Processors
Mayuri Chawla1, Sanjay M Asutkar2, Vijay S. Chourasia3

1Ms. Mayuri Chawla, Department of Electronics and Telecommunication Engineering, Jhulelal Institute of Technology, Nagpur (Maharashtra), India.
2Dr. Sanjay M. Asutkar, Associate Professor, Department of Electronics and Communication Engineering, Manoharbhai Patel Institute of Engineering and Technology, Gondia (Maharashtra), India.
3 Dr. Vijay S. Chourasia, Department of Electronics and Communication Engineering, Manoharbhai Patel Institute of Engineering and Technology, Gondia (Maharashtra), India.
Manuscript received on 07 March 2019 | Revised Manuscript received on 20 March 2019 | Manuscript published on 30 March 2019 | PP: 47-52 | Volume-8 Issue-5, March 2019 | Retrieval Number: D2830028419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: From last few decades computer system becomes an essential part of everyone’s life and day by day its necessity is keep on rising. Computation and processing time is main source & plays a key role to achieve a better performance with very low power & energy consumption. In every electronic devices used in data processing & thus fast data processing requires frequent transfer of data from main memory to CPU. However the performance grid-back of different data-oriented applications is depends on various way of accessing the data cache. Thus, cache memory enhances the performance of processor by tens or hundreds of times much better. Hence the key technique is to diminish overall energy consumption is to vitally shut off the part of a processor’s cache. Reconfigurable cache memory is vital to enhance the store execution and lessens the vitality utilization. In this paper, an audit for past papers related with reconfigurable store memory were given and analyzed it our work .This paper presents our proposed technique that reduces overall power consumption and improved performance in computer system if implemented with the help of some already existing architecture. Paper has introductory section followed by literature review, proposed work, then flow of execution, simulation flow and then results & analysis section which contains observation taken on by doing various simulations. Detailed block diagram describes the working of proposed technique, followed by execution flow diagram that depicts the flow of execution of our proposed technique then simulation flow which depicts the simulation process of technique , then result and analysis sections depicts the partial result of proposed technique ,after that there is a conclusion section followed by future work and limitation of out proposed technique.
Keyword: Cache, Computer System, Pipeline, Memory Architecture, Data Processing.
Scope of the Article: Low-power design