Novel Techniques for Noise-Tolerance in Combinational Critical-Path Circuit Components
Alaaeldin Hafez1, Hanan A. Hosni Mahmoud2

1Alaaeldin Hafez*, Department of Information Systems, College of Computer and Information Science, King Saud University Riyadh, KSA
2Hanan A. Hosni Mahmoud, Department of Computer Science, College of Computer and Information Sciences, Princess Nourah bint Abdulrahman University, Riyadh, KSA
Manuscript received on January 13, 2020. | Revised Manuscript received on January 24, 2020. | Manuscript published on February 10, 2020. | PP: 636-639 | Volume-9 Issue-4, February 2020. | Retrieval Number: D9059029420/2020©BEIESP | DOI: 10.35940/ijitee.D9059.029420
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Abstract: The continued scaling of the device and interconnect in the deep submicron jurisdiction of the complementary metal oxide semiconductor (CMOS) very large scale design (VLSI) has brought many new design challenges and exposed the limitations of the traditional VLSI design. One of the most severe problems in the deep submicron is that the circuit tend to malfunction by producing incorrect outputs in the event of inputs that have glitch. Such noise problem has emerged as the critical reliability problem in the deep submicron, in addition to the power dissipation problem. In this proposal, new research is proposed to counter the noise problem through novel circuit design techniques and methodologies. As we continue in deep submicron, the reliability of such designs is reduced as the output levels of such circuit suffer because of voltage scaling. We present our research along with the results and then describe the further proposed research. The research techniques are described using the combinatorial gates which serve as the critical path component in many designs. Also, an efficient flip-flop CD, that is conditionally discharged when there is no input changes and the input remains high to high, is proposed. This new flip-flop reduces the switching state activity, and is almost glitch-less at the output. The results from our proposed techniques demonstrate at least 2.3x the noise-immunity over the best known results in the literature. 
Keywords: Noise-Immunity, Efficient Flip-Flop, VLSI Design, CMOS
Scope of the Article: Energy Efficient Building Technology