Multi-Core Micro-Controller Architecture with ZLPIC for High Performance Embedded Applications
Kulkarni Rashmi Manik1, S Arulselvi2, B Karthik3

1Kulkarni Rashmi Manik, Research Scholar, Department of ECE, Bharath institute of Higher Education and Research, Chennai (Tamil Nadu), India.
2S.Arulselvi, Associate Professor, Department of ECE, Bharath Institute of Higher Education and Research, Chennai (Tamil Nadu), India.
3B.Karthik, Associate Professor, Department of ECE, Bharath Iinstitute of Higher Education and Research, Chennai (Tamil Nadu), India.
Manuscript received on 07 March 2019 | Revised Manuscript received on 20 March 2019 | Manuscript published on 30 March 2019 | PP: 139-145 | Volume-8 Issue-5, March 2019 | Retrieval Number: E2916038519/19©BEIESP
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Abstract: The main objective is to propose a multi-core architecture for micro-controller implementation, considering availability of various microprocessor cores and advancement in fabrication technology. As it is possible to fabricate 2 million gates per square millimeter at advanced 40nm CMOS fabrication technology and availability of embedded FLASH technology on same process, the innovative multi-core microcontroller can be developed for high performance, low power features. ZLPIC (Zero Latency Programmable Interrupt Controller) module is added along with multi-core to enhance performance. Often embedded micro-controllers need variety of interrupt handling. Zero interrupt latency mechanism is very much required in embedded applications. As long as the interrupt actions are limited and predefined, it is possible to give zero latency response for handling interrupt. A simple device with limited programming model is proposed for achieving zero latency. The logic can be easily integrated with multi-core micro-controller architecture.
Keyword: ARM, CMM (Chip Multi-Core Micro Controller), CMOS, GPIO, IPDE, ISR, Interrupt Latency, NVM, SRAM And ZLPIC.
Scope of the Article: RFID Network and Applications