Optimal Design Approach to Multiplier Unit Using Adaptive Logical Counters
Mohammad Abdul Naveed1, R.P. Singh2

1Mohammad Abdul Naveed, Research Scholar, Sri Satya Sai University of Technology and Medical Science, Bhopal (Madhya Pradesh), India.
2Dr. R.P. Singh, Research Guide, Sri Satya Sai University of Technology and Medical Science, Bhopal (Madhya Pradesh), India.
Manuscript received on 07 March 2019 | Revised Manuscript received on 20 March 2019 | Manuscript published on 30 March 2019 | PP: 322-327 | Volume-8 Issue-5, March 2019 | Retrieval Number: D2682028419/19©BEIESP
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Abstract: Multipliers are the primal constituents of a processing unit. The process of multiplication is carried out using different suggested architectures. Among the developments the common factor observed is the use of recursive register interface in multiplication operation. multiple registers were used in count to buffer the temporary data and gives a new result on addition of these register values. It is needed to minimize the resource requirement to enhance the objective of optimal multiplication operation, in this paper a new low resource adaptive counter based multiplier design is proposed, which minimizes the register requirement by deriving a sub counter logic in multiplier design.
Keyword: Multiplier Design, Adaptive Logical Count, Low Resource Overhead.
Scope of the Article: Optical Link Design