Hustle and Frequency Analysis Based High Speed and Energy Efficient Art Design on Spartan-6 Fugal
Abhishek Kumar1, Bishwajeet Pandey2, D. M Akbar Hussain3, Mohammad Kamrul Hasan4, Pervesh Kumar5, Shabeer Ahmad6

1Abhishek Kumar, SET, Sharda University, India.
2Bishwajeet Pande, Gyancity Research Lab, India.
3D. M Akbar Hussain, Aalborg University, Denmark .
4Dr. Mohammad Kamrul Hasan, Universiti Malaysia Sarawak UNiMAS.
5Pervesh Kumar, Sungkyunkwan University, South Korea.
6Shabeer Ahmad, Gran Sasso Science Institute, Italy.
Manuscript received on 07 March 2019 | Revised Manuscript received on 20 March 2019 | Manuscript published on 30 March 2019 | PP: 1234-1239 | Volume-8 Issue-5, March 2019 | Retrieval Number: E3380038519/19©BEIESP
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Abstract: In this paper our aim is to design an energy efficient UART using different IO Standard. UART known as Universal Asynchronous Receiver Transmitter. It is one of the crucial element in communication system to communicate two michro controller based system. For short distance and low cost data exchange, UART is widely used. The implementation of UART’s with VHDL can be unified into FPGA for the achievement of reliable, and compact data transmission. In this paper, we aregoing to implementan HSTL(High-Speed Transceiver Logic) IOSTANDARD based energy efficient Asynchronous Receiver Transmitter (UART). To achieve speed and high performance, we are using HSTL (High-Speed Transceiver Logic) IOSTANDARD.The HSTL family which we used in this paper are HSTL_I, HSTL_II, HSTL-I_18, and HSTL_II_18 IO Standards. Frequency Scaling technique is one of the best energy efficient technologies for FPGA, which is used in this paper In this paper, it has been analysed the demand for total power dissipation of different IO Standard at different frequency level. We have analysed that the increasing of frequency leads to increase in the clock and IO powerfor different IO standards.
Keyword: FPGA, HSTL, UART, Energy Efficient, Io Standards.
Scope of the Article: Frequency Selective Surface