Implementation of 2D Non-linear Morphological Image Processing on FPGA Based Architecture
K. Sambashivudu1, Md. Javeed2, R. Kiran3

1K.Sambashivudu, M.Tech, Department of VlSI System Design, Ganapathy Engineering College, Warangal (Telangana), India.
2MD. Javeed, M.Tech, Department of VlSI System Design, Ganapathy Engineering College, Warangal (Telangana), India.
3R.Kiran, Asstant Professor, Department of ECE, Ganapathy Engineering College, Warangal (Telangana), India.
Manuscript received on 10 November 2013 | Revised Manuscript received on 18 November 2013 | Manuscript Published on 30 November 2013 | PP: 72-76 | Volume-3 Issue-6, November 2013 | Retrieval Number: F1333113613/13©BEIESP
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Abstract: Image processing requires high computational power and the ability to experiment with algorithms. Recently, reconfigurable hardware devices in the form of field programmable gate arrays (FPGAs) have been proposed as a way of obtaining high performance at an economical price. FPGA technology has become a viable target for the implementation of real time algorithms suited to video image processing applications. Morphing is a Technique used to transfer from one image to another. However, most morphological tools such MATLAB are not suited for strong real-time constraints. The unique architecture of the FPGA has allowed the technology to be used in many applications encompassing all aspects of video image processing. Among those algorithms, linear filtering based on a 2D convolution, and non – linear 2D morphological filters, represent a basic set of image operations for a number of applications. This paper reports on the design and realization of an FPGA based image processing for implementation of morphological image filtering using a FPGA NexysII, Xilinx Spartan 3E, with educational purposes. The system is connected to a USB port of a personal computer, which in that way form a powerful and low-cost design. The FPGA technologies offer basic digital blocks with flexible interconnections to achieve high speed digital hardware realization. The FPGA consists of a system of logic blocks, such as look up tables, gates, or flip-flops and some amount of memory. The image will be transferred from PC to FPGA board using UART serial communication/JTAG cable. After performing the required filtering/processing the result will be transferred back to computer. In PC both the results will be validated. A comparison between results obtained from MATLAB simulations and the described FPGA-based implementation is presented.
Keywords: Morphology, Image Processing Algorithms, Field Programmable Gate Array (FPGA), Filtering, Simulation.

Scope of the Article: Image Processing and Pattern Recognition