Design of a Low Latency and High Throughput Packet Classification Module on FPGA Platform
Anita P1, Manju Devi2
1Anita P*, Research scholar, Department of Electronics & Communication Engineering, TOCE, Bengaluru, India.
2Dr. Manju Devi, Professor & Head, Department of Electronics & Communication Engineering, TOCE, Bengaluru, India
Manuscript received on March 15, 2020. | Revised Manuscript received on March 28, 2020. | Manuscript published on April 10, 2020. | PP: 1468-1474 | Volume-9 Issue-6, April 2020. | Retrieval Number: F4195049620/2020©BEIESP | DOI: 10.35940/ijitee.F4195.049620
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Packet classification method plays a significant role in most of the Network systems. These systems categories the incoming packets in various flows and takes suitable action based on the requirements. If the size of the network is vast and complexity will arise to perform the different operations, which affects the network performance and other constraints also. So there is the demand for high-speed packet classifiers to reduce the network complexity and improve the network performance. In this article, The Bit vector Packet classifier (BV-PC) Module is designed to improve the network system performance and overcome the existing limitation of Packet classification approaches on FPGA. The BV-PC Module contains Packet generation Unit (PGU) to receive the valid incoming packets, Memory Unit (MU) to store valid packets, Header Extractor Unit (HEU) extracts the IP Header address information from the Valid packets, The BV-Based Source and Destination Address (BV-SA, BV-DA) unit receives the IP packet header Information and Process with BV based rule set and aggregates the BV-SA and BV-DA outputs, Priority Encoder encodes the Highest priority BV Rule for the generation of Classified output. The BV-PC utilizes <2% Chip area (slices), works at 509.38MHz, and consumed Less 0.103 W of total Power on Artix-7 FPGA. The BV-PC operates with a latency of 5 clock cycles and works at 815.03Mpps throughput. The BV-PC is compared with existing approaches and provides Better improvements in Hardware constraints.
Keywords: Bit Vector (BV), Packet Classifier, Ruleset, FPGA, Throughput, Packet Generation Unit, Source Address, Destination Address, Latency.
Scope of the Article: Classification