High Speed RC4 Algorithm Based on True Dual Port RAM by using Verilog HDL
Thirupathi Naidu P1, Ashok Kumar V2, Kranthi R3
1Thirupathi Naidu P, Student, Department of ECE, Aditya Institute of Technology & Management, Tekkali, Srikakulam (Andhra Pradesh), India.
2Ashok Kumar V, Associate Professor, Department of ECE, Aditya Institute of Technology & Management, Tekkali, Srikakulam (Andhra Pradesh), India.
3Kranthi R, Associate Professor, Department of ECE, Aditya Institute of Technology & Management, Tekkali, Srikakulam (Andhra Pradesh), India.
Manuscript received on 10 December 2014 | Revised Manuscript received on 20 December 2014 | Manuscript Published on 30 December 2014 | PP: 97-99 | Volume-4 Issue-7, December 2014 | Retrieval Number: G1928124714/14©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents high speed hardware implementation and an area efficient of the RC4 algorithm based on True Dual Port (TDP) RAM. The proposed architecture uses Block RAM (BRAM) implementation to reduce the area and to increase the speed of operation hence throughput. The proposed design uses only one 256 bytes True Dual Port RAM for key stream generation and it needs two clock cycles per one byte. It supports 1 byte to 256 bytes of variable key length and it achieves 71.39 MB/s throughput at 142.78 MHz maximum operating frequency. The True Dual Port RAM RC4 algorithm is implemented in Verilog HDL. The Proposed design is targeted on XC4VFX12-12SF363 Xilinx FPGA and met the operating frequency of 142.78 MHz.
Keywords: True Dual Port RAM, BRAM, CPLD, FPGA, RC4 Algorithm and Stream Cipher.
Scope of the Article: Algorithm Engineering