Design of Hybrid BCD Code Based Parallel Decimal Multiplie
Mahankali1, Pallavi2, V. Sarada3

1Mahankali, Department of University College, Organization, City Country.
2Pallavi, Department of University College, Organization, City Country.
3V.Sarada, Department of University College, Organization, City Country.

Manuscript received on 01 May 2019 | Revised Manuscript received on 15 May 2019 | Manuscript published on 30 May 2019 | PP: 2690-2695 | Volume-8 Issue-7, May 2019 | Retrieval Number: G5819058719/19©BEIESP
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Abstract: By using Three Properties of Binary Coded decimal (BCD) codes, BCD excess-3 code, and the overloaded decimal digit set (ODDS) code the parallel decimal multiplier is existed. In this paper Binary Coded Decimal-4221/5211 Partial Product Reduction block and normal decimal partial product tree using Overloaded Decimal Digit set (ODDS) is presented; it contains a binary Partial Product Reduction block, an unstable size Binary Coded Decimal-4221 counter block and a Binary Coded Decimal-4221/5211 partial product reduction block. These blocks were designed in Verilog language and implemented in FPGA Spartan-6.
Keyword: Parallel Decimal Multiplication, Overloaded BCD Representation, BCD -4221 and 5211, Radix-10 Encoding.
Scope of the Article: Search-Based Software Engineering