A lightweight RSA-based System-on-a-Chip Design for Constrained Application
Richard Boateng Nti1, Kwangki Ryoo2

1Richard Boateng Nti, Department of Communication Engineering, Hanbat National University, Yuseong-Gu Daejeon, South Korea, East Asian.

2Kwangki Ryoo, Department of  Communication Engineering, Hanbat National University, Yuseong-Gu Daejeon, South Korea, East Asian.

Manuscript received on 10 June 2019 | Revised Manuscript received on 17 June 2019 | Manuscript Published on 22 June 2019 | PP: 721-728 | Volume-8 Issue-8S2 June 2019 | Retrieval Number: H11210688S219/19©BEIESP

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The driving force of System-on-a-chip technology has made it possible for smart devices such as tablets and phones perform task that PCs execute though they are much smaller. In this paper, we present a lightweight SoC design embedded with an RSA crypto-engine for low area and low power devices. We present an SoC design which contains the picorv32, a processor developed from the RISC-V ISA, the AMBA bus interconnection for on-chip communication, the RSA core as the hardware accelerator for security usage and peripheral controllers such as the UART, LED and 7-segment. The key components of notice are the picorv32 processor and the RSA modules. Emphasis is made on the efficient design for the RSA design. As a result of a proposed radix-II Montgomery multiplier and modular exponentiation design coupled with resource sharing of submodules, the entire crypto-core yielded significant gains with respect to area complexity. Other units of the RSA such as pseudo-random, primality tester and key generator are optimized to achieve maximal performance in operation. The design involved two developmental stages: software and hardware. The software phase was coded in C, compiled using the GCC into an assembly program. Hardware development on the other hand was accomplished using Verilog HDL at RTL. Synthesis of the Montgomery multiplier and modular exponentiation was carried out using the TSMC 90nm and 130nm CMOS process for comparison with existing systems. Synthesis results of our proposed modular multiplier and modular exponentiation at 250MHz and 452MHz achieved a reduction of 47% and 28% respectively. This system presented is well suitable for area-constrained environment such as the IoT platform.

Keywords: System-on-a-Chip, RSA, Picorv_32, AMBA, Modular Exponentiation, Montgomery Multiplication.
Scope of the Article: Communication