Hardware Architecture of High Speed HEQ for Image Enhancement
Kibum Suh

Kibum Suh, Department of Railway Electrical System, Woosong University, Daejeon, Korea, East Asian.

Manuscript received on 10 June 2019 | Revised Manuscript received on 17 June 2019 | Manuscript Published on 22 June 2019 | PP: 761-766 | Volume-8 Issue-8S2 June 2019 | Retrieval Number: H11270688S219/19©BEIESP

Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper, the hardware architecture of high speed HEQ, which can process full HD image and can be incorporated in small size FPGA, is proposed. In order to verify the efficiency of the proposed architecture, a reference C was constructed and compared with other algorithms. The proposed architecture has similar performance compared with previous existing algorithm and can process image enhancement in high speed. Synthesized FPGA logic has minimum 6.25ns period and can process full HD image sequence at 60frame/sec. The SRAM used is 10752 bits and the number of slice LUT is 119 out of 4420, which is the number of slice LUT for XC6SL9. Unlike the retinex algorithm, which requires pay royalties, the designed modules can be used without royalties, and can be easily ported to small FPGAs. The developed module can be used as a component of a video camera in a DVR system or a surveillance system.

Keywords: Image Enhancement, Retinex, iridix, Small Size FPGA, High Resolution Image.
Scope of the Article: Community Information Systems