Eluding Side Channel Attacks by using Masking 128Bit AES Design
Pallavi1, Seerapu Anil Nagendra2, S V Uma3

1Pallavi*, VLSI And Embedded System (M Tech), RNSIT, Bangalore, India.
2S. Anil Nagendra, VLSI Design(M Tech), GITAM University, Visakhapatnam, India.
3DR. S V Uma , ECE Department, RNSIT, Bangalore, India.
Manuscript received on May 16, 2020. | Revised Manuscript received on June 05, 2020. | Manuscript published on June 10, 2020. | PP: 952-955 | Volume-9 Issue-8, June 2020. | Retrieval Number: H6732069820/2020©BEIESP | DOI: 10.35940/ijitee.H6732.069820
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Advanced encryption standard is detailing for data crypto graphing. The algorithm used universally for cryptography and secure data transmission, the algorithm puissant to intruders, who often attack via side channels. One of the observed attacks was estimate the power implanted in AES core and processed probable scrutinizing to guess the key on multiple iterations. So in order to elude side channel attacks and reduce power consumed in AES standard, design proposed with masking and pipeline scheme. This design helps in shrinking power consumption as compare to AES algorithm and upgrade to withstand from attacks. Another major improvement in the design is LUT’s used for masking and original algorithm almost equal, area phenomenon also solved out. The proposed algorithm implemented in VERTEX-7 FPGA board and simulated using Xilinx Vivado 2015.2 and Modelsim. 
Keywords: AES crypto graphing, side channel attacks, intruder, pipelining, trade-off, S box, Galois fields, cipher, masking.
Scope of the Article: Computer Graphics, Simulation, and Modelling