Partitioning in Three Dimensional Integration Microelectronics using Cuckoo Search Meta-heuristic
Maninder Kaur1, Ashwin Prashar2
1Maninder Kaur, Computer Science and Engineering Department, Thapar Institute of Engineering and Technology, Patiala, India.
2Ashwin Prashar, Computer Science and Engineering Department, Thapar Institute of Engineering and Technology, Patiala, India.
Manuscript received on 02 June 2019 | Revised Manuscript received on 10 June 2019 | Manuscript published on 30 June 2019 | PP: 1308-1316 | Volume-8 Issue-8, June 2019 | Retrieval Number: H7116068819/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Miniaturization and increased integrated system’s complexity in microelectronics have steered three-dimensional VLSI circuit design as a promising technological approach in the field of integrated circuit design. In recent times, three-dimensional integrated circuits (3D ICs) has evolved as an emerging technology that aids in overcoming the interconnect delay and power limitations of 2D ICs. This technology has become the center of attraction among the researchers and IC designers. The key idea behind this technique is to tightly integrate multiple silicon tiers using vertical 3D vias thereby reducing the interconnect length, resistance and capacitance that greatly influence the performance in terms of power and delay. Partitioning is the preliminary step in 3D IC design that maps the whole circuit into different design parts for allocation to different tiers. The current work develops a novel three-dimensional partitioner based on Cuckoo Search Meta-heuristic for partitioning and layer assignment of the netlist in 3D IC design, pertaining to a set of constraints such as inter-tier connections optimization and area balance. The proposed work is implemented on IBM benchmarks in MATLAB environment. The results highlighted reduced number of interconnect count and computational time for the proposed approach in comparison to the Meta –Genetic approach.
Keyword: 3D Partitioner, Cuckoo Search, Layer Assignment, Wire-length Minimization.
Scope of the Article: Search-Based Software Engineering.