Enhanced Scan Segmentation for Low Power DFT
Shalini Pathak1, Mausumi Pohit2, Anuj Grover3

1Amit Kumar Uniyal, Department of Commerce, Graphic Era Deemed To Be University, Dehradun (U.K.), India.
2Shipra Agarwal, Department of Commerce, Graphic Era Deemed To Be University, Dehradun (U.K.), India.

Manuscript received on 30 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 1557-1561 | Volume-8 Issue-9, July 2019 | Retrieval Number: H7428068819/19©BEIESP | DOI: 10.35940/ijitee.H7428.078919
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Excessive test power dissipation during scan testing of an SOC may cause reliability and yield concerns for the circuit under test (CUT). We propose an enhanced scan segmentation method using logic cluster controllability (LoCCo) technique for scan chain stitching to reduce test power efficiently. After LoCCo based scan stitching, since the trailing edge of scan chains contain very less switching transitions, we optimize the number of segments needed. This enables segmentation hardware reduction and still achieve lower power scan test compared to conventional method. Test cases prepared from ITC’99 standard circuits and industrial designs in 40nm CMOS and 28FDSOI technology were used for comparison. LoCCo based scan segmentation gave a shift power reduction of up-to 21.7% over conventional scan segmentation. Up-to 8.6%, shift power gain was observed even with 25% reduced segmentation when enhanced scan segmentation technique is used.
Keywords: Low power DFT, scan stitching, scan segmentation, care bits, DFT.

Scope of the Article: Predictive Analysis