Area Efficient High Speed Vedic Multiplier
Ketan Thakur1, Tripti Sharma2

1Ketan Thakur, Department of ECE, Chandigarh University, Mohali (Punjab), India.

2Tripti Sharma, Department of ECE, Chandigarh University, Mohali (Punjab), India.

Manuscript received on 20 August 2019 | Revised Manuscript received on 27 August 2019 | Manuscript Published on 26 August 2019 | PP: 302-306 | Volume-8 Issue-9S August 2019 | Retrieval Number: I10480789S19/19©BEIESP | DOI: 10.35940/ijitee.I1048.0789S19

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Abstract: Very large scale integration is a process of integrating hundreds of thousands of transistors or devices into a single chip. VLSI can be categorized into two fields Frontend and Backend. Digital VLSI design falls under the Frontend design. Multiplication is an arithmetic operation important for the Digital Signal Processing (DSP) and for processors. Multiplier is the main hardware block for the digital circuit. More than 70% of the applications in a digital circuit are either addition or multiplication. As these operations dominates most of the execution time so we need fast multipliers. The overall objective of a good multiplier is to have high speed, low power consumption unit, less area. Vedic multipliers are the fast multipliers and occupy less area. They are based on the Vedic mathematics sutra “Urdhava-Triyakbhyam” . The paper contain a high speed multipliers and use of different adder structures.

Keywords: VLSI, DSP, Vedic, Multiplier.
Scope of the Article: Energy Efficient Building Technology