A Low Power, Area Efficient Implementation of AES Algorithm
S. Neelima1, R. Brindha2
1S. Neelima, Asst Professor, Gandhiji Institute of Science and Technology, Jaggayyapet. Krishna, Andra Pradesh. India.
2R. Brindha, Former Professor Department of ECE, Faculty of Engineering, Avinashilingam Institute for Home Science and Higher Education for Women, Coimbatore, Tamilnadu, India.
Manuscript received on 10 July 2019 | Revised Manuscript received on 22 July 2019 | Manuscript Published on 23 August 2019 | PP: 1385-1392 | Volume-8 Issue-9S3 August 2019 | Retrieval Number: I32970789S319/2019©BEIESP | DOI: 10.35940/ijitee.I3297.0789S319
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Encryption is a procedure of convert readable information into encoded appearance so that it can’t be interpreted by the intruder. Paper presents the FPGA implementation of a low power, neighborhood efficient AES algorithm for encrypting data. From the results it has been experimental that the enhanced technique has reduced the power consumption and area compared to the existing methods. The implementation is done in 90 nm and 65 nm CMOS technology using Quartus for Cyclone II and Cyclone III.
Keywords: Advanced Encryption Standard, Security, FPGA implementation, Low power, and area efficiency
Scope of the Article: Algorithm Engineering