Temporal Performance Analysis of Enhanced 8 Bit RISC Architecture
Tanaji M. Dudhane1, Ravi T2

1Tanaji M. Dudhane, Department of ETCE, Sathyabama Institute of Science and Technology, Chennai, India.
2Ravi T, Department of Engineering and Communication Engineering, Sathyabama Institute of Science and Technology, Chennai, India.

Manuscript received on 01 July 2019 | Revised Manuscript received on 09 July 2019 | Manuscript published on 30 July 2019 | PP: 3209-3214 | Volume-8 Issue-9, July 2019 | Retrieval Number: I8668078919/19©BEIESP | DOI: 10.35940/ijitee.I8668.078919

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper, we have proposed the development of the Enhanced 8-bit RISC architecture and the temporal performance analysis of the enhanced architecture. The enhanced 8 bit RISC architecture is powered with the additional block called as Co-operative Arithmetic and Logical Unit (CALU). The 8 bit core is designed using FPGA as SPARTAN-6 XC65LX9-3TQG144. The purpose of designing is to integrate number of instructions with additional instructions, which are 16 bits with keeping all original instructions execution having 8 bit format. We have designed the enhanced of 8 bit processor for improvement in speed as well as to speedup of the execution cycle, so that improvement in clock cycles per second for execution of an instruction. The Enhanced RISC architecture is fully compatible with the original core along with old instruction set. The CALU is designed to enhance the multi-byte capabilities of the core. The performance improvement in terms of the clock cycle savings has been recorded. The performance enhancement of average 71% has been recorded by the Enhanced core. The Enhanced RISC core has been developed and simulated on Xilinx Vivado 2017.3.
Keywords: CALU, FPGA, RISC, Temporal.

Scope of the Article: High Performance Computing