A Novel NOR-Type TCAM Deploy Dual-VT cell with OR-Type Cascade Match-Line Structure
Rahul Nigam1, Santosh Pawar2

1Rahul Nigam*, Electronics and Communication Engineering Department, Dr. A.P.J Abdul Kalam University, Indore, India.
2Santosh Pawar, Principal School of Engineering and Dean R & D, Dr. A.P.J. Abdul Kalam University, Indore, India.
Manuscript received on July 11, 2020. | Revised Manuscript received on July 21, 2020. | Manuscript published on August 10, 2020. | PP: 35-39 | Volume-9 Issue-10, August 2020 | Retrieval Number: 100.1/ijitee.J73760891020 | DOI: 10.35940/ijitee.J7376.0891020
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: We look over improvements in the schemes of large size content addressable memory (CAM). A CAM is a very important device that executes the routing table function within a single clock cycle in network router to transmit information over the network. CAMs are particularly popular in network switches to classify and sending information packets, they are also helpful in other different applications that require fast information retrieval from routing table. The primary CAM configuration challenge is to decrease power dissipation related with the lot of parallel activity in memory circuitry during search operation. As innovation going on in technology scaling, it continues minimizing the dynamic power dissipation of CAMs, however it also rises the leakage current of transistors. Thus, the static power is turning into a noteworthy bit of the whole power dissipation in CAMs. Here, we introduced a procedure which advantageous for high capacity Ternary Content Addressable Memory (TCAM) that minimize the static power dissipation in SRAM storage cell part and speed up activity in searching part of TCAM cell. We also divide whole memory into equivalent segments which improve performance of our design. We examine the different schemes and introduced the trade-offs of applying the techniques. Simulation and design have done by using Tanned EDA V.16 tool. For recreations of Low power TCAM structures we utilized predictive technology model (PTM) 45nm for high performance (HP) and low power (LP), which incorporate metal gate, high-k and stress effect of CMOS technology. 
Keywords: Dual-VT, High capacity, Low power, OR-type Match-line, TCAM.