Integer N Synthesizer Design for LoRa Transceivers
Vítor Fialho

Vitor Fialho*, ADEETC, Instituto Superior de Engenharia de Lisboa and Centre of Technology and Systems, Lisbon, Portugal.

Manuscript received on August 19, 2021. | Revised Manuscript received on August 24, 2021. | Manuscript published on August 30, 2021. | PP: 101-106 | Volume-10, Issue-10, August 2021 | Retrieval Number: 100.1/ijitee.J944708101021 | DOI: 10.35940/ijitee.J9447.08101021
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Abstract: This paper presents the study and design of an Integer N synthesizer model for three LoRa ISM bands: 430 MHz 868 MHz and 915 MHz. The proposed topology is composed by two voltage controlled oscillators working in two different bands. The presented model uses the same phase-frequency detector, charge pump and loop filter. This study is focused on dynamic and steady-state analysis in order to infer the synthesizer stability and bandwidth. The performed study shows that the settling time for all bands is less than 40 µs for a bandwidth of 102 kHz
Keywords: LoRa, Settling Time, Synthesizer, Transceiver