Implementation of Low Power High Speed Adder’s using GDI Logic
Addanki Purna Ramesh

Addanki Purna Ramesh, Professor, Department of ECE, Vishnu Institute of Technology, Bhimavaram, India. 
Manuscript received on 25 August 2019. | Revised Manuscript received on 15 September 2019. | Manuscript published on 30 September 2019. | PP: 1291-1298 | Volume-8 Issue-11, September 2019. | Retrieval Number: J95470881019/2019©BEIESP | DOI: 10.35940/ijitee.J9547.0981119
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Abstract: Addition is a vital arithmetic operation and is the base of other arithmetic operations such as multiplication, subtraction and division. Adder is a digital circuit that does addition of binary numbers. The 1-bit full adder is the basic block of an arithmetic unit. In VLSI, there are many efficient techniques to design digital circuits. Some of the techniques are Pass Transistor logic (PTL), Complementary metal oxide semiconductor (CMOS) and Transmitter gate (TG). There are several adder designs implemented to reduce the power. However, each design undergoes from precise disadvantage. The adder design with good driving capability requires more power and the design with more delay which consumes less power. In this paper 8-bit Carry Increment Adder (CIA), Carry Bypass Adder (CBA), Carry Skip Adder (CSKA), Carry Look Ahead Adder (CLA), Kogge Stone Adder (KSA), Han Carlson Adder (HCA), and Brent Kung Adder (BKA) are implemented using Gate Diffusion Input (GDI) logic. These designs are simulated and implemented using Tanner tool. The result shows that CBA, CLA, and KSA designs using GDI logic are more efficient compared to CMOS logic in view of power consumption, delay, and area (transistors count) respectively.
Keywords: Adder, Addition, GDI, CMOS, Power consumption
Scope of the Article: Low-power design