Novel Pipelined Scalable Systolic Multiplier Based on Irreducible All-One Polynomials
S. Srinivas1, E. John Alex2, Prasad Janga3
1Mr. S.Srinivas, PG Scholar, Department of ECE, CMR Institute of Technology, Hyderabad, Telangana, India.
2Dr. E.John Alex, Professor, Department of ECE, CMR Institute of Technology, Hyderabad, Telanagana, India.
3Dr.Prasad.Janga, Professor, Department of ECE, CMR Institute of Technology, Hyderabad, Telanagana, India.
Manuscript received on 11 September 2019 | Revised Manuscript received on 20 September 2019 | Manuscript Published on 11 October 2019 | PP: 617-625 | Volume-8 Issue-11S September 2019 | Retrieval Number: K110309811S19/2019©BEIESP | DOI: 10.35940/ijitee.K1103.09811S19
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A planned productive structure issued for the systolic execution of authoritative based limited field duplication over G F(2 m) in light of final 56-bit AOP is proposed in this work. We extricated a recursive increase calculation and utilized it to plan an intermittent and confined piece level reliance outline (DG) for systolic registering. The intermittent piece level DG is changed into a very smal grained DG, and the pipe coating is utilized for snappier mapping into a parallel systolic design. It doesn’t require any overall correspondences for measured decline, in contrast to most current developments. The suggested bit-parallel systolic structure is similar to the parallel systolic structure, however the quantity of registers is altogether lower.
Keywords: Pipelining, Elliptic curve cryptography (ECC), error-control-coding, very large scale integration (VLSI).
Scope of the Article: Network Coding