Implementation of Montgomery Multiplier using Scalable Architecture
Satya Ranjan Das1, Badri Narayan Sahoo2
1Satya Ranjan Das, Dept. of Computer Sc. Eng, Siksha O Anusandhan Deemed to be University, Odisha, India.
2Badri Narayan Sahoo, Dept. of Electronics & Communication Eng, Siksha O Anusandhan Deemed to be University, Odisha, India.
Manuscript received on 15 September 2019 | Revised Manuscript received on 23 September 2019 | Manuscript Published on 11 October 2019 | PP: 966-970 | Volume-8 Issue-11S September 2019 | Retrieval Number: K117809811S19/2019©BEIESP | DOI: 10.35940/ijitee.K1178.09811S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper describes the methodology and design of a scalable Montgomery multiplication module. This multiplier can manipulate any number of bits without any limitation. The size of a word depends upon the area which is available and also the performance which is required. After the general architecture is described, hardware organization is analyzed for implementing parallel computation and the discussions on design tradeoffs are done for recognising best configuration for hardware.
Keywords: Montgomery multiplication, pipelining, processing element, modular multiplication.
Scope of the Article: Computer Architecture and VLSI