Two Parallel Pipelined FFT Architecture After Third Stage for Low Complexity and Latency
G. Prasanna Kumar1, Pushpa Kotipalli2, B.T.Krishna3

1Prasanna Kumar G, Department of Electronics and Communication Engineering, JNTUK, Kakinada (A.P), India.
2Krishna.B.T, Professor, Department of Electronics and Communication Engineering, JNTUK, Kakinada (A.P), India.
3Pushpa Kotipalli, Professor, Department of Electronics and Communication Engineering, Shri Vishnu Engineering College for Women, Bhimavaram (A.P), India.

Manuscript received on 23 August 2019. | Revised Manuscript received on 13 September 2019. | Manuscript published on 30 September 2019. | PP: 918-922 | Volume-8 Issue-11, September 2019. | Retrieval Number: K15580981119/2019©BEIESP | DOI: 10.35940/ijitee.K1558.0981119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: TComplexity is the major issue in the development of pipelined Fast Fourier Transform (FFT) structure. A novel parallel pipelined FFT design constructed for low complexity and Latency. The proposed structure efficiently uses pipeline and parallel pipeline in the design. The first three stages of the structure follow the pipelining and from fourth stage there are two parallel paths simultaneously compute four complex additions, the first three single path stages that reduces complexity, parallel pipeline stages at the end of structure also reduces the Latency. The proposed structure is an optimized solution to reduce the trade-off between Latency and complexity. The comparative performance of the proposed structure with several other existing structures shows that it has Low latency with small cost of hardware.
Keywords: Ecomplexity, FFT, parallelism, pipelined
Scope of the Article: