An Innovative Low Power Reversible ALU for Quantum Processor using QCA
Rajinder Tiwari1, Vikas Rajiv2, Preeta Sharan3, Anil Kumar4
1Rajinder Tiwari*, Research Scholar, Department of ECE, Amity University, Lucknow, India.
2Vikas Rajiv, Department of ECE, The Oxford College of Engineering, Bangalore, India. Email:
3Preeta Sharan, Department of ECE, The Oxford College of Engineering, Bangalore, India.
4Anil Kumar, Department of ECE, Amity University, Lucknow, India.
Manuscript received on September 16, 2019. | Revised Manuscript received on 24 September, 2019. | Manuscript published on October 10, 2019. | PP: 2903-2909 | Volume-8 Issue-12, October 2019. | Retrieval Number: K17380981119/2019©BEIESP | DOI: 10.35940/ijitee.K1738.1081219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Landauer stated that “For irreversible computation each loss in information leads to loss of kTln2 joules of heat energy”. This has led to considerable interest in reversible logic. We know that ALU is the most basic part in any processor. Processor quality is determined based on its speed of operation. But, as the size of a processor decreases we face problems like power dissipation and greater delays. So, this paper presents an ALU implemented using reversible logic. This design is a simple way to reduce power dissipation and delay to a certain extent. Verilog HDL programming has been used to make this design. We have used XILINX and CADENCE tool to simulate this model and obtain power and delay analysis.
Keywords: ALU, Reversible Computing, Power Dissipation, Xilinx, Cadence, VHDL, Quantum Processors.
Scope of the Article: Quantum Computing