Hardware Acceleration of SVM classifier using Zynq SoC FPGA
Vidhyapathi CM1, Maheshwar Reddy M2, Nikhil Reddy T3, Alex Noel Joseph Raj4, Kathirvelan J5
1Vidhyapathi CM, SENSE Dept., Vellore Institute of Technology, Vellore, India.
2Maheshwar Reddy, SENSE Dept., Vellore Institute of Technology, Vellore, India.
3Nikhil Reddy, SENSE Dept., Vellore Institute of Technology, Vellore, India.
4Alex Noel Joseph Raj, Department of Electronics Engineering, Shantou University, China.
5Kathirvelan J, SENSE Dept., Vellore Institute of Technology, Vellore, India. Manuscript received on September 16, 2019. | Revised Manuscript received on 24 September, 2019. | Manuscript published on October 10, 2019. | PP: 2280-2288 | Volume-8 Issue-12, October 2019. | Retrieval Number: L25621081219/2019©BEIESP | DOI: 10.35940/ijitee.L2562.1081219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Support Vector Machines (SVM) is one of the most commonly used the state-of-the-art supervised machine learning algorithm for various classification problems. It provides high accuracy rate compared to other classification algorithms. However, When SVM is modelled only using Software, it is a time consuming algorithm due to its high computational complexity. This makes the algorithm to be not suitable for embedded real time applications. We propose a new hardware software co-design approach to achieve the real time performance by accelerating the computationally intensive classifier part of the algorithm as a custom hardware Intellectual Property (IP) core. In this paper, a novel Support Vector Machine (SVM) linear classifier is modelled as a custom hardware Intellectual Property (IP) core using High Level Synthesis (HLS). The developed IP core is optimized for latency and hardware resource utilization by applying various directives of HLS tool. The synthesis results of the IP core for Skin segmentation dataset is reported. The proposed hardware software co-design approach is implemented in real time on Zynq-7000 XC7Z020 System on Chip (SoC) field programmable gate arrays (FPGA). A detailed comparative results of proposed hardware software co-design approach and the complete software approach is reported in this work for Iris and Breast cancer dataset. A promising result of 18x speedup is achieved using SVM classifier hardware IP compared to is software counterpart.
Keywords: SVM, Hardware-Software Co-simulation, HLS, IP, SoC, FPGA.
Scope of the Article: Simulation Optimization