Potential Use of RTL Co-Simulation
1S.Karthik, Department of ECE, SRMIST, Vadapalani, Chennai India.
2K.Priyadarsini, Department of CSE, VISTAS, Pallavaram, Chennai India.
Manuscript received on September 13, 2019. | Revised Manuscript received on 23 September, 2019. | Manuscript published on October 10, 2019. | PP: 586-588 | Volume-8 Issue-12, October 2019. | Retrieval Number: L34631081219/2019©BEIESP | DOI: 10.35940/ijitee.L3463.1081219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper’s objective is to highlight the potential use of C/RTL Co-Simulation and application of it in satisfying the time constraints involved in verification of industrial, complex, monolithic. Co-Simulation performed in Xilinx software has provided a platform for further analysis of designs. Steps before performing co-simulation has provided statistical data about how much resources the system design requires which can be further analyzed, part-by-part, using profiling method. The profiling allows demarcation of a distinctive line between resource-intensive processes and time-intensive processes. A further study into this matter would purge the need of resource-intensive and time-consuming devices. This could be a small step towards attaining a level of production where the outcome is a better device and error-less production of these devices.
Keywords: Monolithic, Constraints, Complex, Stylin.
Scope of the Article: Production