Efficient FPGA Implementation of Human Detection from Video Sequences
Sharath S1, Rangaraju H G2
1Sharath.S*, Department of Electronics and Communication Engineering, Government College of Engineering, Krishnarajapete, Mandya, Karnataka, India.
2Rangaraju H G, Department of Electronics and Communication Engineering, Govt. Sri Krishnarajendra Silver Jubilee Technological Institute, Bengaluru, Karnataka, India.
Manuscript received on March 15, 2020. | Revised Manuscript received on March 27, 2020. | Manuscript published on April 10, 2020. | PP: 242-248 | Volume-9 Issue-6, April 2020. | Retrieval Number: F3690049620/2020©BEIESP | DOI: 10.35940/ijitee.F3690.049620
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Detection of Human is a vital and difficult task in computer vision applications like a police investigation, vehicle tracking, and human following. Human detection in video stream is very important in public security management. In such security related cases detecting an object in the video, sequences are very important to understand the behavior of moving objects which normally used in the background subtraction technique. The input data is preprocessed using a modified median filter and Haar transform. The region of interest is extracted using a background subtraction algorithm with remaining spikes removed using threshold technique. The proposed architecture is coded using standard VHDL language and performance is checked in the Spartan-6 FPGA board. The comparison result shows that the proposed architecture is better than the existing method in both hardware and image quality.
Keywords: Adaptive Threshold, Background Subtraction, FPGA Implementation, Human Detection, Modified Median Filter.
Scope of the Article: Energy Efficient Building Technology