Design of Power Efficient divide by 2/3 Counter using E-TSPC based Flip Flops
J.Suganthi1, N.Kumaresan2, K.Anbarasi3

1Dr.J.Suganthi, Professor and Head, Department of CSE, Hindusthan College of Engineering and Technology, Coimbatore, India.
2N.Kumaresan, Assistant Professor, Department of ECE, Anna University of Technology, Coimbatore, India.
3K.Anbarasi, PG Scholar, Department of ECE, Anna University of Technology, Coimbatore, India.

Manuscript received on July 01, 2012. | Revised Manuscript received on July 05, 2012. | Manuscript published on July 10, 2012. | PP: 158-161 | Volume-1, Issue-2, July 2012. | Retrieval Number: C8893019320/2012©BEIESP
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Abstract: High speed and low power are two major challenges for modern communication circuit designs. A frequency divider is a good example that requires balance between the two sides. An extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design is proposed in this paper which can be used for low supply voltage and low power consumption applications. By using a wired OR scheme only one transistor is needed to implement both the counting logic and the mode selection control. This can enhance the working frequency of the counter due to a reduced critical path between the E-TSPC flip flops. 
Keywords: D flip-flop (DFF), frequency divider, frequency synthesizer, Extended TSPC