Low Power Oriented Full Search Block Based Motion Estimation (LP-FSBME) Architecture Using Power Efficient Adder Compressor For H.265 Coding Techniques
B. Hemamalini1, R. Ramadhurai2, S. Mahaboob Basha3

1B. Hemamalini, Department of Applied Electronics Engineering, Gojan School of Business and Technology, Nallur (Tamil Nadu), India.

2R. Ramadhurai, Assistant Professor, Department of Electronics Engineering, Gojan School of Business and Technology, Nallur (Tamil Nadu), India.

3S. Mahaboob Basha, Assistant Professor, Department of Electronics Engineering, RMK Engineering College, Nallur (Tamil Nadu), India.

Manuscript received on 22 November 2019 | Revised Manuscript received on 03 December 2019 | Manuscript Published on 14 December 2019 | PP: 67-71 | Volume-9 Issue-1S November 2019 | Retrieval Number: A10161191S19/2019©BEIESP | DOI: 10.35940/ijitee.A1016.1191S19

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: H.265 coding is known as HIGH efficiency video coding (HEVC). This is most successful video compression standard and extended from H.264/MPEG-4 advanced video coding (AVC) for same level of video quality. However, H.265 improved better video quality for same bit rate. In video coding, motion estimation (ME) is determined the motion vector from adjacent frames. Various algorithms have been introduced by many researchers to accomplish low power oriented ME. However, low power oriented full search block based motion estimation (LP-FSBME) algorithm gives accurate results. Architecture of sum of absolute difference (SAD) is used an adder tree to accumulate the processing elements. Power efficient 16:2 adder compressors in SAD architecture reduce the power dissipation rather than convention adders in SAD architecture. The hardware implementation of proposed method is done in Xilinx Virtex 7 FPGA XC7VX1140T device with speed grade 1 in Xilinx software version 14.5 tool, developed in Verilog Hardware Description Language (Verilog-HDL), and simulated in ISE simulator for tennis, BQ terrace and Kimono videos with the resolution of 1080×720 pixels with 30fps.

Keywords: ADDER COMPRESSOR, Xilinx Virtex 7 FPGA, VERILOG.
Scope of the Article: Low-power design