Design and Performance Analysis of Low Power High Speed CNTFET Binary Content Addressable Memory Cell for Next Generation Communication Networks
A. Gangadhar1, K.Babulu2
1A.Gangadhar*, Research Scholar, ECE Department, JNTUK, Kakinda, India.
2K.Babulu, Professor, ECE Department, JNTUK, Kakinda, India.
Manuscript received on November 15, 2019. | Revised Manuscript received on 20 November, 2019. | Manuscript published on December 10, 2019. | PP: 8-15 | Volume-9 Issue-2, December 2019. | Retrieval Number: A4016119119/2019©BEIESP | DOI: 10.35940/ijitee.A4016.129219
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) cells are proposed. The adiabatic logic is integrated with the proposed BCAM cells to improve performance. The performance of proposed BCAM cells is presented for various CNTFET parameters such as number of tubes, chirality vector, pitch value, dielectric constant and dielectric materials. It also explores the optimum set of CNTFET parameters for low power and high speed characteristics of the proposed BCAM cells. Simulation results show an improvement in the average power and delay of proposed BCAM cells. The average power of the proposed BCAM cells is in the order of nano watts while the CMOS based BCAM cells is in the order of micro watts. The delay of the proposed BCAM cells is improved by 56.4 %. All simulations are conducted for both CMOS and CNTFET based BCAM cells in HSPICE at 32 nm technology.
Keywords: Carbon Nanotube Field Effect Transistor, Content Addressable Memory, Optimum Parameter Set.
Scope of the Article: Communication