Multi-Core Eight Bit Ternary Content-Addressable Memory Design Based Image Learning System
S. Bhargav Kumar
S.Bhargav Kumar*, Electronics & Communication Engineering (ECE) Department, Jawaharlal Nehru Technological University Hyderabad, Hyderabad, India.
Manuscript received on October 12, 2019. | Revised Manuscript received on 22 October, 2019. | Manuscript published on November 10, 2019. | PP: 4037-4041 | Volume-9 Issue-1, November 2019. | Retrieval Number: A5303119119/2019©BEIESP | DOI: 10.35940/ijitee.A5303.119119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this research work, the image is learned to find features to make use of during its analysis and a genetic apices based low power Ternary Content-Addressable Memory (TCAM) is designed to implement the proposed image learning system. A technique called Content Matching Search Register is proposed in this work to perform the image learning operations in proposed TCAM architecture. This paper proposes an ImOFF algorithm for image analysis. The focus of this multi-core TCAM (MC-TCAM) is to make fast computations and search based designs. The focus application of this research work is in the design of low power On-board Embedded-VLSI chip to perform image analysis. Proposed multi-core eight bit Ternary TCAM (MCEB-TCAM) is analyzed using IC design tools in 90nm technology, using Verilog hardware description language and usage of Cadence for layout generation and parasitic extraction of the circuit components.
Keywords: Feature learning, TCAM, Image Analysis, Cadence, pixels.
Scope of the Article: Deep Learning