Performance Analysis of Double Gate Hetero Junction Tunnel Fet
Anjani Devi N1, Ajaykumar Dharmireddy2, Sreenivasa Rao Ijjada3

1Anjani Devi N, Assistant Professor, Department of ECE, GRIET, Hyderabad (Telangana), India. 

2Ajaykumar Dharmireddy, Assistant Professor, Department of ECE, Sir CR Reddy college of Engineering, Eluru (Andhra Pradesh), India. 

3Sreenivasa Rao Ijjada, Assistant Professor, Department of EECE, GITAM Institute of Technology, Vishakhapatnam (Andhra Pradesh), India. 

Manuscript received on 23 November 2019 | Revised Manuscript received on 11 December 2019 | Manuscript Published on 30 December 2019 | PP: 232-234 | Volume-9 Issue-2S3 December 2019 | Retrieval Number: B10581292S319/2019©BEIESP | DOI: 10.35940/ijitee.B1058.1292S319

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Abstract: In this paper, a novel heterojunction tunnel field-effect transistor (HTFET) using Sentaurus technology computer-aided design (TCAD) simulations has been presented. The InAs/GaSb compound materials are used in both single gate heterojunction TFET (SG-HTFET) and Double gate heterojunction TFET (DG-HTFET) with SiO2 gate oxide layer to increase performance of the device.The implemented SG-HTFET and DG-HTFET device are increase the TFET’s cross-sectional tunnel area. This result develops the subthreshold swing (SS) by 2.45 times, drive current (ION) is close to 10-6 A/µm, leakage current (IOFF) is close to 10-17 A/µm and also diminish the ambipolarity of the device compared to the TFET.

Keywords: Ambipolarity, Heterojunction TFET (HTFET), Double Gate Hetrojunction Transistor (DG-HTFET), Tunnelling field-effect Transistor (TFET).
Scope of the Article: Performance Evaluation of Networks