MFMW: Modified Floor planning with Minimum Wire length
N.Subbulakshmi1, R.Chandru2, R.Manimegalai3
1Dr.N.Subbulakshmi*, Associate Professor, Malla Reddy Engineering College(A), Telangana, India.
2R. Chandru, Assistant Professor, Sri Ramakrishna Engineering College, Coimbatore, India.
3Dr.R.Manimegalai, Professor, PSG Institute of Technology and Applied Research, Coimbatore, India.
Manuscript received on November 13, 2019. | Revised Manuscript received on 21 November, 2019. | Manuscript published on December 10, 2019. | PP: 4212-4213 | Volume-9 Issue-2, December 2019. | Retrieval Number: B6667129219/2019©BEIESP | DOI: 10.35940/ijitee.B6667.129219
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Abstract: Floor planning is one of the most critical phases inVLSI circuit design. The module alignment has a substantial concentration on the minimization of chip area and total wirelength in slicing floorplan. At foremost, the disadvantages of dead space are investigated and an instinctive and profligate method is proposed to find the equitable part of component. Then, a tormenting for standardized expression is improved to produce new solution, and the proposed simulated annealing algorithm which improves design efficiency is opted for the best floorplan solution. The proposed MFMW method attains less area on the commonly used AMI33 and AMI 49 benchmark circuits.
Keywords: Floorplanning, Wirelength, VLSI
Scope of the Article: VLSI Algorithms