Design of A High Performance 4-Bit Ternary Multiplier using CNTFET
P.Venkat Laxman1, Ranjan K. Senapati2, L.Dharma Teja3

1P.Venkat Laxman*, M.Tech (VLSI System design) VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad
2Ranjan K. Senapati, Professor, Department of Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology , Hyderabad, India
3L.Dharma Teja, Assistant Professor, Department of ECE, VNR Vignana Jyothi Institute of Engineering Technology from June.

Manuscript received on November 15, 2019. | Revised Manuscript received on 21 November, 2019. | Manuscript published on December 10, 2019. | PP: 3106-3111 | Volume-9 Issue-2, December 2019. | Retrieval Number: B7477129219/2019©BEIESP | DOI: 10.35940/ijitee.B7477.129219
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Abstract: In digital world, digital circuits are influenced by binary logic. Ternary logic which follows the multiple valued logic concept for designing the logic circuits which is an great alternate to the normal binary logic due to its less power consumption and chip area is reduces. Carbon Nano-tube Field-Effect Transistors (CNTFET) is selected to implement the ternary logic circuits due to its mechanical , electrical and thermal properties. The unique feature of CNTFETs has the potential of getting required threshold voltage by varying the diameter of carbon nano-tubes that makes them as a best appropriate type for implementing the ternary logic. In this paper a 4-Bit Ternary Multiplier is designed using 1-Bit ternary multiplier by CNTFET 32nm technology node and simulated in Hspice tool. The proposed 1-Bit multiplier has 10% less delay and 18% less power than the 1-Bit multiplier proposed by Srivasu et al. 
Keywords: Cntfet, Mosfet, Ternary Logic.
Scope of the Article: Digital System and Logic Design