Gain Error end DNL for Testing ADCs: Optimization in Time Domain
Manish Jain1, R P Kumawat2

1Dr. Manish Jain*, Associate Professor, EEE Department, Mandsaur University, Mandsaur, M.P.
2Prof. R P Kumawat, Assistant Professor, EEE Department, Mandsaur University, Mandsaur, M.P.
Manuscript received on December 15, 2019. | Revised Manuscript received on December 21, 2019. | Manuscript published on January 10, 2020. | PP: 891-894 | Volume-9 Issue-3, January 2020. | Retrieval Number: B7821129219/2020©BEIESP | DOI: 10.35940/ijitee.B7821.019320
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Abstract: Optimization in ADC is an important component which predicts overall accuracy of a system using it. Signals are in real time nature and it is necessary to convert these signals in digital form to interpret with digital form of signals and microcomputer based systems. ADC is used to carry out these conversions process from analog to digital. Determination of parameters of an ADC such as DNL, INL, SNR and ENOB are necessary for complete dynamic analysis and characterization of ADC. In frequently, application prerequisite input to an Analog to digital converter is time varying which requires determination of its parameters at corresponding frequency and different test conditions In order to test an ADC, it is necessary to first determine its code transition levels. Further Gain error, DNL are estimated using code transition level based on histogram technique. If there is an code transition level error introduced then effect of this error leads to error in estimate of gain, offset, DNL and ENOB. Further estimation of variance in different parameter values is analyzed in the proposed work. 
Keywords: Analog-to-digital converter, Effective No. of Bit, Histogram Technique, Offset Error, Gain Error.
Scope of the Article: Discrete Optimization