Buried Powered 4t Sram with Improved Write Margin
K. Manohar1, M. Sri Hari2, MD. Basheer Ahamad3, Sai Krishna4, P. Lakshman5

1K. Manohar*, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P, India.
2M. Sri Hari, Department of Electronics and Communication Engineering ,Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P, India
3MD. Basheer Ahamad, Department of Electronics and Communication Engineering ,Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P, India.
4Sai Krishna, Department of Electronics and Communication Engineering ,Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P, India
5P. Lakshman Department of Electronics and Communication Engineering ,Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P, India.
Manuscript received on December 15, 2019. | Revised Manuscript received on December 20, 2019. | Manuscript published on January 10, 2020. | PP: 2248-2351 | Volume-9 Issue-3, January 2020. | Retrieval Number: B7868129219/2020©BEIESP | DOI: 10.35940/ijitee.B7868.019320
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Abstract: The main intention of this paper is to understand clearly about the high performance of 4T-SRAM with an improved write margin. the power consumption is often reduced considerably by using a buried power rail (BPR) to the SRAM cell, which reduces the resistance of bit line and word line. The write margin is often increased by the fine standardization of metal dimensions within the SRAM cell. Conventionally, 4T-SRAM cell offers high speed and fewer space compared to 6T-SRAM cell. 4T-SRAM is actualized using 130nm CMOS Technology. 
Keywords: SRAM, Performance, Write Margin, Buried Power Rail ,Static-Noise-Margin (SNM).
Scope of the Article: Measurement & Performance Analysis